In multi-core systems, it is often desirable for the individual cores (e.g., microprocessors, digital signal processors (DSPs), and the like) to share a peripheral device, rather than being coupled to their own dedicated devices. That is, while it is common in prior art systems to include two peripheral devices, where each is coupled to a corresponding core, such configurations may be replaced by a system as shown in the block diagram of FIG. 1. As illustrated, a prior art dual-core system might include two cores 102 and 104 sharing a peripheral 120 through bus arbiter 110 and shared peripheral bus 112, which might include any number of such peripherals.
The illustrated architecture is unsatisfactory in a number of respects. For example, the software driver and hardware support required outside of the peripheral becomes increasingly more complicated as cores are added, as each core typically includes its own copy of the driver, and each driver requires knowledge of all other cores within the system. This can cause a security risk, as one core may stop the other core from accessing the peripheral, resulting in a “denial of service” attack. Furthermore, typical peripherals are capable of generating only a single interrupt. This single interrupt is then either multiplexed between the two interrupt control handlers (associated with each core) or sent to both handlers. Furthermore, in the illustrated architecture, one of the cores may cause the peripheral to enter an error state, which will then prevent the second core from accessing that peripheral.
Accordingly, it is desirable to provide systems and methods for simplifying the sharing of peripherals between cores in multi-core systems. Other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.